1. Technical Field
The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to semiconductor devices including redistribution line structures and methods of fabricating the same.
2. Description of the Related Art
In the semiconductor field, a major focus of technology research is to minimize the size of a semiconductor device. Also in the semiconductor device packaging field, consumer demand for small-size computers and portable electronic devices is increasing significantly. Semiconductor device packages which provide a high pin count in a small size, including a Fine Pitch Ball Grid Array (FBGA) package and a Chip Scale Package (CSP), are being developed.
The semiconductor device packages, for example, the FBGA package and the CSP, have a physical advantage in that they are small in size and light in weight. However, they do not have equivalent quality and reliability as compared with a conventional plastic package. Further, the cost of raw materials and the cost of the processing required for production of these packages are relatively high at this point in development. A Micro-ball Grid Array (micro BGA; μBGA) package, which is a typical example of recent chip scale package designs, has better characteristics than the FBGA package or the CSP. However, it also lags behind the conventional plastic package in reliability and cost.
In order to overcome these disadvantages, a Wafer Level Chip Scale Package (wafer level CSP; WL-CSP) has been developed. The WL-CSP uses redistribution or rerouting of bonding pads of a semiconductor chip to provide packaging flexibility.
In a semiconductor device fabrication (FAB) process, the WL-CSP redistributes another pad, larger in size, in place of the bonding pad on the semiconductor chip. Then, an external connection terminal, for example, a solder ball or a bonding wire, is formed on the redistributed pad.
FIG. 1 and FIG. 2 are cross-sectional views of semiconductor devices including conventional redistribution line structures.
Referring to FIG. 1, a semiconductor device may include a semiconductor chip 10, a passivation layer pattern 14, a first insulation layer pattern 16, a redistribution line pattern 20, and a second insulation layer pattern 22.
The semiconductor chip 10 includes an active surface on which a bonding pad 12 is disposed. The passivation layer pattern 14 covers the active surface of the semiconductor chip 10 and exposes a portion of a surface of the bonding pad 12. The first insulation layer pattern 16 is disposed on the entire surface of the passivation layer pattern 14. The redistribution line pattern 20 is extended on the first insulation layer pattern 16 while being electrically connected to the exposed portion of the surface of the bonding pad 12. The second insulation layer pattern 22 includes a land opening 23 exposing another portion of a surface of the redistribution line pattern 20 which is spaced apart from the bonding pad 12.
An Under Barrier Metal (UBM) pattern (not shown) is interposed on the exposed portion of the surface of the bonding pad 12, the bonding pad 12 which overlaps the redistribution line pattern 20, and on the first insulation layer pattern 16. The redistribution line pattern 20 is electrically connected to an external circuit through a connection means (not shown), for example, a solder ball or a bonding wire provided in the land opening 23.
The passivation layer pattern 14 alone is insufficient to protect the semiconductor chip 10 from various stresses or damage inflicted by the external environment during a redistribution process or other package assembly processes. Therefore, the first insulation layer pattern 16 is further provided on the passivation layer pattern 14 in order to protect the semiconductor chip 10 from stresses inflicted from the external environment.
Referring to FIG. 2, a semiconductor device includes a semiconductor chip 110, a passivation layer pattern 114, a first insulation layer pattern 116, a second insulation layer pattern 118, a redistribution line pattern 120, and a third insulation layer pattern 122.
The semiconductor chip 110 includes an active surface on which a bonding pad 112 is disposed. The passivation layer pattern 114 covers the active surface of the semiconductor chip 110 and exposes a portion of a surface of the bonding pad 112. The first insulation layer pattern 116 is disposed on the passivation layer pattern 114. The first insulation layer pattern 116 has a fuse cutting opening 117. The fuse cutting opening 117 exposes the passivation layer pattern 114 over a fuse 111 included within the semiconductor chip 110. The second insulation layer pattern 118 is disposed on the entire surface of the first insulation layer pattern 116, while filling the fuse cutting opening 117. The redistribution line pattern 120 is extended on the second insulation layer pattern 118, while being electrically connected to the exposed portion of the surface of the bonding pad 112. The third insulation layer pattern 122 has a land opening 123 exposing another portion of a surface of the redistribution line pattern 120 which is spaced apart from the bonding pad 112.
An Under Barrier Metal (UBM) pattern (not shown) is interposed on the exposed portion of the surface of the bonding pad 112 overlapping with the redistribution line pattern 120 and on the second insulation layer pattern 118. The redistribution line pattern 120 is connected to an external circuit through a connection means (not shown), for example, a solder ball or a bonding wire provided in the land opening 123.
As described with reference to FIG. 1, the first insulation layer pattern 116 is further provided on the passivation layer pattern 114 in order to protect the semiconductor chip 110 from various stresses inflicted from the external environment during a redistribution process for fabricating a Wafer Level Chip Scale Package (wafer level CSP; WL-CSP).
The fuse 111 may be provided to repair the semiconductor chip 110 if the semiconductor chip 110 is identified as defective during a testing process. Generally, the redistribution process is performed after defective semiconductor chips 110 are repaired. If the second insulation layer pattern 118 is not disposed between the first insulation layer pattern 116 and the redistribution line pattern 120, a defect may occur in the semiconductor chip 110 having the fuse cutting opening 117 during an etching process for fabricating the UBM pattern, which is one of the processes of fabricating the redistribution line pattern 120. Also, during a plating process for forming the redistribution line pattern 120, an Electrical Die Sorting (EDS) bonding pad (not shown) may be inadvertently electrically connected with the redistribution line pattern 120. Accordingly, a process for forming the second insulation layer pattern 118 is required, before performing a process for forming the redistribution line pattern 120.
In the semiconductor devices including redistribution line structures as described above, a multilayer of insulation layer patterns is formed on a wafer. Therefore, the warpage of the wafer where semiconductor chips are formed may increase as a result of differences in the Coefficient of Thermal Expansion (CTE) between the wafer and the multilayer of insulation layer patterns. Such warpage of the wafer not only makes it difficult to perform redistribution and subsequent processes, but also causes the reliability of the semiconductor device to decrease, resulting from stress inflicted on semiconductor chips. The present invention addresses these and other disadvantages of the conventional art.